Contemporary computing systems, even those classified as personal computers, are steadily growing in complexity. As additional functionality is added to such systems through the addition of new and/or improved circuits and peripheral devices, a common problem that arises is where to place such circuit/peripheral within the context of the goal of improving overall system performance. To make use of the functionality of such peripheral it must of course be able to communicate with other circuits/devices in the system through some form of data/control bus. Typical contemporary computing systems include a number of data and control busses, including in some cases all or some of the following: (a) a host (processor) bus; (b) a memory access bus; (c) a primary system bus; (d) an expansion bus; (e) secondary system busses, etc. This differentiation is necessary and desirable because various components used with such busses have different performance characteristics; thus, for overall system performance it is generally the case that components of equivalent performance/characteristics are grouped on a single "bus."
One of the more common system busses used today is the so-called Peripheral Component Interconnect (PCI) bus. This bus is increasing in popularity, primarily because it is supported by a large number of personal computer system vendors as the standard of choice. A description of the characteristics and interface requirements of the PCI bus can be found at, among other places, a library of technical materials maintained by Intel at its website: www.intel.com or at developer.intel.com. Another popular but older standard bus is the Industry Standard Architecture (ISA) bus. The ISA bus is still used, even in high performance computing systems today, because many of the peripheral devices which use such bus are not able (they lack the performance capability) to reside on the PCI bus. These include, for example, such circuits and devices as floppy disk drive controllers, keyboard controllers, real time clocks, serial ports, parallel ports, game ports, general purpose I/O (GPIO), and ROM access. While there are efforts to move such circuits and other devices to higher performance busses (such as USB and 1394 Firewire), this is not cost-effective for many vendors, because it is more expensive to interface such low-cost devices to the higher performance bus systems. Accordingly, it is expected that ISA bus capability will still be needed for many more years to come.
At present, a conventional method for coupling disparate busses within a computer system is through the use of so-called "bridge" controllers. For example, a typical prior art device is the Intel 82371 AB component, which incorporates functionality for interacting and maintaining data flow between a variety of different busses, including a PCI bus, an ISA bus, an IDE bus, a USB bus, etc. A data sheet dated April 1997 describing such device, commonly known as a "South Bridge," and its operation, is also provided at the URL noted above, and such data sheet (and any later updates to the extent such are added) is incorporated herein by reference. It is expected that eventually such South Bridges will eliminate the ISA interface in order to reduce costs, and as part of an effort to prod lower performance device designers into conforming their products to the newer higher performance/functionality bus standards.
A problem that has not been addressed so far, therefore, is how to incorporate ISA bus functionality in computing systems that lack such capability in a conventional South Bridge device. A major hurdle that needs to be overcome is the fact that the PCI/ISA interface (wherever such is located) must be able to receive configuration information at start-up. Typically, this occurs by means of a system BIOS passing configuration parameters to a host CPU, which in turn executes an ISA configuration cycle at initialization, and after such cycle is claimed by the South Bridge, the CPU passes on such configuration information to the ISA interface within the South Bridge. Accordingly, it is apparent that in the absence of this interface in the South Bridge, the latter will not claim the ISA cycle, and any BIOS parameters will not be passed on to any ISA devices in the system. Thus, it is not possible with conventional architectures to pass on system configuration information in a computing system that requires ISA capability, but which includes an upgraded expansion bus bridge controller lacking an ISA interface.
A related problem arises from the fact that a conventional PCI device must first receive initialization information from a BIOS before they can proceed with many housekeeping functions. This is very undesirable, and leads to increase set up times for such devices, reducing overall system response and performance.